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Downscaled Assembly of Vertically Interconnected Devices



Microsystem packages get smaller and smaller - promising not only enhanced mobility of more interactive and user-friendly assistants, but also reduced cost: Waferlevel technologies have the potential to 30% or more savings on an electronic device. The technological challenges, however, are high. The European FP6 project DAVID addresses some of these, in particular related to hybrid inertial sensor systems with their very specific requirements regarding to vacuum control and material stress reduction.




 
Please check out the final project report:   3,952kB

Chip-to-wafer integration approach

The figure above shows a Chip-to-Wafer concept that unites micromachined silicon sensors (top chip, shown as a transparent block) with a microelectronic chip (bottom). Within the ultra-small hermetic cavity between the chips, a getter film (black layer) covers the ASIC surface and provides a lifetime vacuum inside the package. This allows the sensor's proof mass to operate in a resonant mode with controlled damping. The chip stack is protected against fracturing by a wafer molding process. Through-silicon vias redistribute all contacts to solder balls on the backside, thus forming a chip-scale system in a package.

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