First of all: What is a MEMS?

This handy abbreviation stands for "Micro Electro-Mechanical System", but today it is more specifically used for the low-level implementation of such a system - the lowest integration level would be a monolithic system containing mechanical and electronic structures on a single chip. From marketing point of view, this may sometimes be an interesting approach. However, as requirements grow, the economic boundary conditions for the respective MEMS and CMOS part of the system diverge.

A more favorable approach is therefore a compact, threedimensional hybrid integration by chip stacking and enhanced vertical signal routing. Waferlevel packaging (WLP) combines the possibly smallest implementation form with the economical benefits of wafer batch processing.

The picture above shows a current System-in-Package (SiP) technology realized by STMicroelectronics: A gyroscope MEMS is hermetically encapsulated on wafer level, using a passive cap wafer without any other functionality. Together with the electronic circuits in the ASIC placed on top of the MEMS device, a smart sensor system is realized. However, this approach is based on discrete device handling and a complexe wire bonding scheme.

The next step as being targeted by the DAVID project consists of further reducing time and material efforts by using direct bonding methods for the mechanical, hermetic and electrical joining of MEMS and ASIC. Two approaches are examined: A purely wafer-bonding oriented approach (1) is compared to a "semi-WLP" concept (2), placing singulated MEMS devices on top of a CMOS wafer:

1) Wafer-to-Wafer (W2W) bonding of MEMS and ASIC: A temporary carrier wafer allows MEMS thinning to 100µm. The residual thickness should be sufficient for processing, while in the final package the MEMS chip is additionally supported by the ASIC. STMicroelectronics decided for this integration technology and upgraded all their MEMS production lines for the 8" wafer format that they equally use for their respective ASIC lines.

2) Chip to wafer (C2W): The approach chosen by Fraunhofer ISIT is driven by the current global heterogeneity of wafer formats and supply chains. Processing singulated MEMS provides a high degree of independence for choosing ASIC foundries and technologies. The probably lower manufacturing yield may be compensated by assembling only good devices - which is naturally not possible in wafer bonding.